This invention relates generally to semi-conductor memory, and more specifically to a simplified scheme for accessing sequential data in a non-volatile memory such as an EEprom or Flash EEprom memory and handling the defects therein.
Semi-conductor memory is formed as an integrated circuit (IC) device with a two-dimensional array of memory cells arrayed in rows and columns. Each cell contains a transistor which can be put into one of its conduction states designating one of the memory states.
Computers and digital systems typically use magnetic disk drives for permanent mass storage of data. However, disk drives are disadvantageous in that they are bulky and in their requirement for high precision moving mechanical parts. Consequently, they are not rugged, and are complicated and prone to reliability problems, as well as consuming significant amounts of power.
Solid state memory devices such as Random Access Memory (RAM), Read only Memory (ROM), Programmable read-only memory (PROM), UV Erasable PROM (UVEPROM), Electrically Erasable programmable read-only memory (EEprom) and Flash EEprom do not suffer from these disadvantages. However, in the case of RAM, the memory is volatile, and requires constant power to maintain its memory. Consequently, RAMs are typically used as temporary working storage.
ROM, EEprom and Flash EEprom are all non-volatile solid state memories. They retain their memory even after power is shut down. However, ROM and PROM cannot be reprogrammed. UVPROM cannot be erased electrically. On the other hand, EEprom and Flash EEprom have the further advantage of being electrically writable (or programmable) and erasable. Nevertheless, conventional EEprom and Flash EEprom have a limited lifetime due to the endurance-related stress the device suffers each time it goes through an erase/program cycle. The endurance of a Flash EEprom device is its ability to withstand a given number of program/erase cycles. The physical phenomenon limiting the endurance of conventional EEprom and Flash EEprom devices is trapping of electrons in the active dielectric films of the device. During programming, electrons are injected from the substrate to the floating gate through a dielectric interface. Similarly, during erasing, electrons are extracted from the floating gate to the erase gate through a dielectric interface. In both cases, some of the electrons are trapped by the dielectric interface. The trapped electrons oppose the applied electric field in subsequent program/erase cycles thereby causing the programmed threshold voltage to shift to a lower value and the erased threshold voltage to shift to a higher value. This can be seen in a gradual closure in the threshold voltage "window" between the "0" and "1" states. Beyond approximately 1.times.10.sup.4 program/erase cycles the window closure can become sufficiently severe to cause the reading circuitry to malfunction. If cycling is continued, the device eventually experiences catastrophic failure due to a ruptured dielectric. This typically occurs at between 1.times.10.sup.6 and 1.times.10.sup.7 cycles, and is known as the intrinsic breakdown of the device. Thus, with use, defects tend to build up in the memory array and typically the devices are rendered unreliable after 10.sup.3 to 10.sup.4 write/erase cycles. Traditionally, EEprom and Flash EEprom are used in applications where semi-permanent storage of data or program is required but with a limited need for reprogramming.
Physical defects in memory devices give rise to defective cells. Data becomes corrupted whenever it is stored in the defective cells. In conventional memory devices such as RAM and magnetic disks, any physical defects arising from the manufacturing process are corrected at the factory.
It is the usual practice in semi-conductor memories to have redundant memory cells built into the chip. Those defective cells discovered after fabrication are discarded and remapped to these redundant cells in the array. The remapping is usually done by hard wiring at the factory. The device is then assumed to be perfect and there is little or no provision for replacing defective cells resulting from physical defects that appear later during normal operation. Error corrections mainly rely on schemes using error correction codes (ECC) which typically correct a limited number of random errors.
Similarly for EEprom or Flash EEprom devices, defects initially detected after fabrication must be treated. Subsequently, ECC may be used to correct a limited number of random errors. However, the nature of these devices is such that they tend to have more and more cell failures with increasing write/erase cycling while cell failures are largely unaffected by read cycles. If the device is used in applications going through many write/erase cycles, the errors from the defective cells that accumulate will eventually overwhelm the ECC and render the device unreliable.
Conventional handling of defects in solid-state memories are inadequate for EEprom devices in at least two respects. First, there is no effective provision for detecting and handling defects on-the-fly. Secondly, the scheme where redundant rows and columns are used to replace defective ones is inefficient. In this scheme the whole row or column is discarded and remapped even if it contains only a single defective bit. While this is very simple defect management, the number of memory bits wasted are quite material for each defect. This scheme is less acceptable for EEprom devices with higher instances of initial defects. Moreover, if the new defects are to be detected and remapped, more rows and columns will need to be mapped out and eventually reducing the memory size substantially.
Another way of treating defects in EEprom and Flash EEprom is to use schemes similar to defect remapping in disks. In the normal disk system the medium is divided into cylinders and sectors, the sector being the basic unit in which data is stored. A controller is used to manage the operations of the disk and handle defect remapping. Before use, the medium must be initialized (or "formatted") to remap the defects. The system is partitioned into the various sectors. The sectors containing the defects are identified and are marked as bad and not to be used by the system. This is done in several ways. A defect map table is stored on a particular portion of the disk to be used by the interfacing controller. Normally, it is located both in the drive directory and in the header field of a data sector. In addition, the bad sectors are marked as bad by special I.D. and flag markers. When the defect is at an address, the data that would normally be stored there is placed in an alternative location. The requirement for alternative sectors makes the system assigns spare sectors at some specific interval or location. This reduces the amount of memory capacity and is a performance issue in how the alternative sectors are located. Also, the alternative sector remapping is not necessarily sequential with the rest of the data. Generally a sophisticated and expensive controller with microprocessor intelligence is required to handle this type of defect management. An example of defect mapping in EEprom system is disclosed in copending U.S. patent application Ser. No. 337,566, filed Apr. 13, 1989, entitled "Flash EEprom System." The copending application is assigned to the same assignee of the present application and the disclosure of which is hereby incorporated by reference.
Accordingly it is an object of the present invention to provide a memory system without the above-mentioned disadvantages.
It is another object of the invention to provide a simple and low cost memory system for storing sequential data.
It is another object of the invention to provide an EEprom or Flash EEprom system for storing sequential data.
It is another object of the invention to provide a solid-state memory system capable of handling defects detected during use of the device.
It is another object of the invention to provide a simplified and low cost controller only for writing sequential data in an EEprom or Flash EEprom system.
It is another object of the invention to provide a simplified and low cost controller only for writing and reading sequential data in an EEprom or Flash EEprom system.